1. Field of the Invention
This invention relates to a process for fabricating the stacked trench capacitor (STC) of a dynamic random access memory (DRAM), particularly to the process for fabricating the STC structures which are electrically isolated between trenches.
In the present invention, the side wall of the trench, which is encapsulated by a thermal oxide layer, is covered with a side-spacer silicon layer by deposition and subsequent anisotropic dry etch of the CVD silicon. Since the oxide film which is not protected by a side-spacer silicon layer is removed by wet etch, only the side wall of the trench is covered by an oxide/silicon bilayer. The oxide film serves as an insulating layer to eliminate the trench-to-trench leakage current. The electrical isolation is also improved by ion-implantating the dopants underneath the trenches. Further, since the inventive capacitor structure consists of a sloped shape of trench side wall and has no sharp edges, electrical weak spots of the capacitors can be eliminated.
2. Description of Related Art
In order to realize the stacked capacitors for a high density DRAM, a shallow trench is made into a silicon substrate to increase the capacitor area, hence increasing the capacitance. Conventional processing procedures are as follows:
First, as shown in FIG. 1 A, the CVD oxide 10 and poly silicon films 11 are sequentially deposited on the gate 1. As shown in FIG. 1 B, a trench 2 is made by opening the contact window and etching down into a silicon substrate 9 using reactive ion etch (RIE). A poly-silicon layer 4 which serves as a storage node is deposited by CVD, and doped using ion implantation or diffusion from dopant vapor source, as shown in FIG. 1 C. And then, a capacitor area is defined by photo and etch. Finally, as shown in FIG. 1 D, the thin dielectric 6 layer is formed on the storage node poly silicon. Finally, the entire capacitor area is covered by poly-silicon. Finally, the entire capacitor area is covered by poly-silicon 7 for the opposite electrode. In the conventional art, the subsequent high temperature processes after doping the poly-silicon layer 4 lead to out diffusion of dopant from the poly-silicon layer to silicon substrates 9 forming a diffused region 12 around the trench. Formation of diffused region in contact with drain junction increases the contact area between capacitor and the junction.
However, in the conventional art described above, the presence of the dopant diffused regions 12 around the trenches cause a significant leakage current between trenches as shown in FIG. 1 E, which is a cross sectional view taken along line A--A in FIG. 1 F. The problem of leakage current between trenches becomes more significant as the spacing of the trenches decreases and/or the depth of the trenches increases. Another drawback of this structure is that since a vertical shape of the trench is formed after deposition of poly-silicon layer 4, the thin dielectric layer 6 formed later has electrical weak spots at the sharp edges in the bottom part of the trench. Therefore, this capacitor structure causes leakage current between the capacitor electrodes, and hence degrading the reliability of the capacitor.